Traditionally, verification is performed using only rules-based approaches. For example, design rule check (DRC) is performed by checking the geometric properties of as-designed polygons in the design against a set of rules in a designated rule deck. However, the as-designed features may be significantly different from the as-manufactured features once lithography, etch, chemical mechanical planarization (CMP), and other processes are applied to actually manufacture the product. Therefore, two significant problems with the rules-only approach are (1) since the as-manufactured circuit features may differ from the as-designed circuit features, this causes inaccuracies in the verification results and (2) the rules themselves are determined for the as-designed features, and may therefore be overly-pessimistic or overly-optimistic relative to the as-manufactured features.